Method for producing a semiconductor device

ABSTRACT

A producing method of the present invention includes (i) forming a wiring line above a semiconductor substrate, (ii) forming an insulating layer above the semiconductor substrate and the wiring line, (iii) forming an opening penetrating the insulating layer in the insulating layer with respect to a portion above the wiring line, (iv) forming a barrier layer whose surface is formed of a material A, so as to cover a surface of the insulating layer and an inner surface of the opening, (v) forming a metal layer made of a first metal on the barrier layer, and (vi) depositing a second metal inside the opening by a plating, thus forming a via plug containing the second metal. A rest potential P A  of the material A with respect to the second metal is larger than a rest potential P M  of the first metal with respect to the second metal.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method for producing a semiconductor device provided with a via plug.

[0003] 2. Description of Related Art

[0004] In integrated semiconductor devices, it is necessary to embed metal plugs into vias and grooves of interlayer insulating layers. A material used for the metal plug in some cases is copper, which has a low resistance, a high melting point and less tendency toward electro-migration.

[0005] As a method for forming the metal plug, a method using Chemical Mechanical Polishing (CMP) has been studied. The conventional method for forming the metal plug using CMP will be described, with reference to FIGS. 3A to 3E.

[0006] First, a structure shown in FIG. 3A is formed as follows. A silicon oxide layer 101 (hatching is omitted) is formed on a semiconductor substrate 100 made of silicon. A tantalum nitride layer 102 and a wiring line 103 made of copper are formed on the silicon oxide layer 101. A silicon nitride layer 104 is formed so as to cover the silicon oxide layer 101 and the wiring line 103. On the silicon nitride layer 104, a silicon oxide layer 105 and a resist 106 are formed.

[0007] Next, as shown in FIG. 3B, the silicon oxide layer 105 is etched with respect to a portion above the wiring line 103, thus forming an opening 107. Then, the silicon nitride layer 104 in the opening 107 is removed by a reactive ion etching technique. Thereafter, the resist 106 is removed.

[0008] Subsequently, as shown in FIG. 3C, a tantalum nitride layer 108 and a seed layer 109 are formed by sputtering. The tantalum nitride layer 108 serves as a barrier layer for preventing copper of the seed layer 109 from being diffused into the silicon oxide layer 105. The tantalum nitride layer 108 is formed on an inner surface of the opening 107 and a surface of the silicon oxide layer 105. The seed layer 109 serves as a cathode when being plated with copper by electroplating. The seed layer 109 is made of copper and formed so as to cover the entire surface of the tantalum nitride layer 108.

[0009] Next, as shown in FIG. 3D, the seed layer 109 is plated with copper by electroplating, thus forming a copper layer 110.

[0010] Thereafter, as shown in FIG. 3E, the copper layer 110 and the tantalum nitride layer 108 that are located on the silicon oxide layer 105 are removed by CMP, thus forming a via plug 111 made of copper.

[0011] However, the conventional producing method has had a problem that, when forming the copper layer 110 by electroplating, voids 113 a and 113 b are formed easily as shown in FIG. 3D. Especially when the opening 107 has a diameter of less than 0.25 μm, the voids 113 a and 113 b are generated considerably.

[0012] The voids 113 a and 113 b are generated because the seed layer 109 does not have a uniform thickness. The seed layer 109, which is formed by sputtering, has an overhanging thick portion A and a thin portion B located on a side wall of the opening 107, as shown in FIG. 3C. An attempt to reduce the thickness of the portion A results in no seed layer 109 formed on the portion B. On the other hand, an attempt to increase the thickness of the portion B brings about a still thicker portion A. The void 113 a is formed because the portion A is thick. The void 113 b is formed because there is no seed layer 109 in the portion B. As described above, since it is difficult to form a seed layer having a uniform thickness on the tantalum nitride layer 108 as the barrier layer, the conventional producing method has been likely to have voids generated in the via plug 111. The voids 113 a and 113 b cause a lower reliability due to electro-migration or stress-migration and a higher resistance of wiring.

SUMMARY OF THE INVENTION

[0013] With foregoing in mind, it is an object of the present invention to provide a method for producing a semiconductor device provided with a via plug having less voids.

[0014] In order to achieve the above-mentioned object, a method for producing a semiconductor device of the present invention includes processes of (i) forming a wiring line above a semiconductor substrate, (ii) forming an insulating layer above the semiconductor substrate and the wiring line, (iii) forming an opening penetrating the insulating layer in the insulating layer with respect to a portion above the wiring line, (iv) forming a barrier layer whose surface is formed of a material A, so as to cover a surface of the insulating layer and an inner surface of the opening, (v) forming a metal layer made of a first metal on the barrier layer, and (vi) depositing a second metal inside the opening by a plating, thus forming a via plug containing the second metal. A rest potential P_(A) of the material A with respect to the second metal is larger than a rest potential P_(M) of the first metal with respect to the second metal. In the producing method described above, the surface of the barrier layer is formed of the material having a high rest potential. Thus, when the via plug is formed by the plating, the second metal is deposited on the barrier layer at a high speed. Consequently, it is possible to prevent the formation of the voids in the via plug.

[0015] In the above-described producing method of the present invention, the barrier layer may include a first layer and a second layer formed on the first layer; the second layer being made of the material A, and the first layer being made of a material B that has a smaller diffusion coefficient for the first metal and the second metal than the material A. With this embodiment, it is possible to prevent the metal contained in the via plug from being diffused through the barrier layer into the insulating layer, thus lowering reliability. Since copper is easily diffused into the insulating layer made of a material such as silicon oxide, this structure is particularly preferable when the metal contained in the via plug is copper.

[0016] In the above-described producing method of the present invention, the plating may be an electroplating, and in the process (v), the metal layer may be formed in a portion above the insulating layer and at a bottom of the opening alone. With this embodiment, it is possible to prevent the formation of overhang (see FIG. 3C) on the metal layer, and thus the formation of the voids in the via plug particularly can be suppressed. Also, since the metal layer can be formed easily by a conventional sputtering or vapor deposition, it becomes easier to produce a semiconductor device.

[0017] In the above-described producing method of the present invention, the material A may be metal nitride, and the method may further include a process of nitriding a surface of the barrier layer after the process (iv) and before the process (v). With this embodiment, it is possible to further raise the rest potential on the surface of the barrier layer, and thus the formation of the voids in the via plug particularly can be suppressed.

[0018] In the above-described producing method of the present invention, the first metal and the second metal may be copper. With this embodiment, it is possible to produce a semiconductor device easily in a low cost manner.

[0019] In the above-described producing method of the present invention, the material A may be titanium nitride.

[0020] In the above-described producing method of the present invention, the material B may be tantalum or tantalum nitride. With this embodiment, it is possible to produce a semiconductor device with a particularly high reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIGS. 1A to 1G illustrate producing processes in an example of a method of the present invention for producing a semiconductor device.

[0022]FIG. 2 illustrates one process in another example of the method of the present invention for producing the semiconductor device.

[0023]FIGS. 3A to E illustrate producing processes in an example of a conventional method for producing a semiconductor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The following is a description of an embodiment of the present invention, with reference to the accompanying drawings.

[0025]FIGS. 1A to 1G are sectional views illustrating producing processes in an example of a method of the present invention for producing a semiconductor device.

[0026] First, as shown in FIG. 1A, an insulating layer 12 (hatching is omitted) provided with a concave portion 12 a is formed on a surface of a semiconductor substrate 11. A diffusion preventing layer 13 and a wiring line 14 are formed in the concave portion 12 a. In this manner, the wiring line 14 is formed above the semiconductor substrate 11.

[0027] Circuit elements (not shown in the figure) such as a transistor element and a capacitive element are formed on the semiconductor substrate 11. For the semiconductor substrate 11, a substrate commonly used for semiconductor devices, for example, a Si substrate, a GaAs substrate or a SOI (Silicon On Insulator) substrate can be used. The insulating layer 12 is made of, for example, silicon oxide. The diffusion preventing layer 13 prevents metal contained in the wiring line 14 from being diffused, and is made of, for example, tantalum nitride or titanium nitride. The wiring line 14 is formed for connecting the circuit elements. The wiring line 14 is made of metal, for example, copper, aluminum or a copper-alluminum alloy. The diffusion preventing layer 13 and the wiring line 14 can be formed by a common method, for example, a combination of photolithography, sputtering and etching.

[0028] Next, as shown in FIG. 1B, a diffusion preventing layer 15, an insulating layer 16 and a resist 17 are formed sequentially on the semiconductor substrate 11 and the wiring line 14. The diffusion preventing layer 15 prevents metal contained in the wiring line 14 from being diffused, and is made of, for example, silicon nitride. The insulating layer 16 is made of, for example, silicon oxide or an inorganic or organic material with a low dielectric constant. As the inorganic material with a low dielectric constant, HSQ (Hydrogen silsesquioxane) can be used. As the organic material with a low dielectric constant, polyarylether-based material such as SILK (registered trademark) or FLARE (registered trademark) can be used. The resist 17 is provided with an opening. The diffusion preventing layer 15 and the insulating layer 16 can be formed by, for example, sputtering or CVD. The resist 17 is made of, for example, photocurable resin and can be patterned by photolithography.

[0029] Then, as shown in FIG. 1C, a part of the insulating layer 16 is removed using the resist 17 as a mask, so that the insulating layer 16 with respect to a portion above the wiring line 14 is provided with an opening 18 penetrating the insulating layer 16. The resist 17 is then removed. The insulating layer 16 can be removed by, for example, dry-etching. The width of the opening 18 is, for example, about 0.15 μm to 0.5 μm. The depth of the opening 18, that is, the thickness of the insulating layer 16 is, for example, about 0.6 μm to 1.5 μm. The resist 17 can be removed by ashing and chemical cleaning.

[0030] Subsequently, as shown in FIG. 1D, the diffusion preventing layer 15 in the opening 18 is removed, so that the wiring line 14 at the bottom of the opening 18 is exposed. The diffusion preventing layer 15 can be removed by reactive ion etching in which the etching selective ratio between the diffusion preventing layer 15 and the insulating layer 16 is high. During this process, metal oxide such as copper oxide sometimes is formed on the surface of the exposed wiring line 14. This metal oxide may be removed, for example, by a heat-treatment in a reducing atmosphere such as H₂ or a mixed gas of H₂ and He inside a reactor.

[0031] Next, as shown in FIG. 1E, a barrier layer 19 is formed so as to cover a surface of the insulating layer 16 and an inner surface of the opening 18, and then a metal layer 20 made of a first metal is formed on a part of the barrier layer 19. The barrier layer 19 can be formed by, for example, Chemical Vapor Deposition (CVD). It is preferable that, after removing the metal oxide formed on the surface of the wiring line 14, the barrier layer 19 is formed without exposing the semiconductor substrate 11 to the air. A material of the barrier layer 19 will be described later. The barrier layer 19 outside the opening 18 has an average thickness, for example, in the range of 20 nm to 50 nm. It is preferable that the barrier layer 19 inside the opening 18 has an average thickness of at least 10 nm. The barrier layer 19 may be formed of a plurality of layers. FIG. 2 illustrates a process corresponding to that of FIG. 1E in the case where the barrier layer 19 is formed of two layers. The barrier layer 19 in FIG. 2 includes a first layer 19 a and a second layer 19 b formed on the first layer 19 a. A material of the first layer 19 a and the second layer 19 b will be described later.

[0032] When a metal film 21 (which will be described later) is formed by electroplating, the metal layer 20 serves as a cathode. In this case, since the plating is performed by applying an electric potential between an anode and the cathode, it is preferable that the metal layer 20 is formed of a low-resistance material. When the metal film 21 is formed by electroless plating, the metal layer 20 serves to prevent the metal film 21 from peeling off. As the first metal, which is the material of the metal layer 20, copper, niobium, a copper-niobium alloy, gold, silver or platinum can be used, for example. The metal layer 20 has an average thickness, for example, in the range of 100 nm to 500 nm, preferably, 150 nm to 300 nm. More specifically, a metal layer made of copper with an average thickness of 150 nm can be used.

[0033] When the metal film 21 is formed by electroplating, it is preferable that the metal layer 20 is formed in a portion other than a side wall portion of the opening 18 as shown in FIG. 1E. In other words, it is preferable that the metal layer 20 is formed in a portion above the insulating layer 16 and at the bottom of the opening 18 alone. The metal layer 20 may be formed on the entire surface of the barrier layer 19. Also, when the metal film 21 is formed by electroless plating, the metal layer 20 may be formed above the insulating layer 16 alone. The metal layer 20 can be formed by, for example, sputtering or vapor deposition. With such a method, the metal layer 20 can be formed easily in the portion other than the side wall portion of the opening 18. It is preferable that, after forming the barrier layer 19, the metal layer 20 is formed without exposing the semiconductor substrate 11 to the air.

[0034] Next, as shown in FIG. 1F, a second metal is deposited inside the opening 18 and on the barrier layer 19 and the metal layer 20 by plating, so as to form the metal film 21 made of the first metal and the second metal. The second metal is, for example, copper, silver or gold. The metal layer 20 becomes a part of the metal film 21. The metal film 21 includes a via plug 21 a formed inside the opening 18. As described above, the via plug 21 a containing the second metal can be formed on the barrier layer 19 inside the opening 18. The first metal and the second metal may be the same or different. They can be a combination of the above-described materials selected freely, and the first metal/the second metal can be a combination such as copper/copper, niobium/copper or gold/copper, for example.

[0035] Subsequently, as shown in FIG. 1G, a portion of the barrier layer 19 and the metal film 21 with respect to the outside of the opening 18 is removed by Chemical Mechanical Polishing. In this manner, the via plug 21 a embedded in the opening 18 is completed. Thereafter, a semiconductor device is completed by a general semiconductor process according to the semiconductor device to be produced.

[0036] In the following, the material of the barrier layer 19 will be described. At least a surface of the barrier layer 19 is formed of a specific material (referred to as a material A in the following). The rest potential P_(A) of the material A with respect to the second metal is larger than the rest potential P_(M) of the first metal with respect to the second metal. In other words, the surface of the barrier layer 19 is formed of a material on which the second metal is deposited more easily than the first metal. When the first and the second metals are the same, P_(M)=0.

[0037] When the first metal is copper, the rest potential P_(A) of the material A with respect to copper preferably is at least 100 mV, and more preferably is at least 250 mV. For the material A, titanium, tungsten, titanium nitride or tungsten nitride can be used, for example. Among these materials, titanium nitride can be formed by Chemical Vapor Deposition using an inexpensive material gas.

[0038] The inventors measured rest potential values of various materials with respect to copper. The result of these measurements is shown in Table 1. TABLE 1 Layer Rest Sample thickness Formation After potential No. Material (nm) method treatment (mV) 1 TaN 35 IMP None −78 to −71 2 TaN 35 IMP 450 ° C., −55 to −50 5 min. 3 Ti 30 PVD None +130 to +140 4 TiN 35 PVD None +260 to +265 5 TiN 35 PVD 450 ° C., +280 to +290 5 min. 6 W 30 PVD None +134 to +135 7 WN 35 PVD None +112 to +115 8 WN 35 PVD 450 ° C., +116 to +120 5 min. 9 TaN + 35 + 10 IMP + PVD None +107 to +110 Ti

[0039] In Table 1, IMP in the column of Formation method stands for Ionized Metal Plasma method. PVD stands for Physical Vapor Deposition. The After treatment column indicates the conditions of heat-treatment in a nitrogen atmosphere after the film formation. In addition, “TaN+Ti” of Sample 9 indicates the case where a Ti layer is formed on a TaN layer.

[0040] The result shown in Table 1 indicates that the rest potential of tantalum with respect to copper and that of tantalum nitride with respect to copper are both negative. The reason the voids 113 a and 113 b are generated when copper is deposited using tantalum nitride 108 as the barrier layer in the conventional producing method is considered to be because the rest potential of tantalum nitride with respect to copper is negative. On the other hand, the rest potentials of titanium, titanium nitride, tungsten and tungsten nitride were all positive and larger than 100 mV. Accordingly, these materials are preferable as a material of the barrier layer in the case where the second metal is copper.

[0041] When the barrier layer 19 has a structure shown in FIG. 2, the second layer 19 b is made of the material A. The first layer 19 a is made of a material B that has a smaller diffusion coefficient for the first metal and the second metal than the material A. Since the rest potential value is determined by a relative relationship between two metals in contact with each other, the rest potential of the barrier layer 19 in this case is determined by the material A of the second layer 19 b. When the material A is titanium or titanium nitride, tantalum or tantalum nitride can be used as the material B, for example.

[0042] In the producing method of the present invention, since the barrier layer 19 whose surface is formed of the material A is used, metal is deposited more easily on the barrier layer 19 than on the metal layer 20 when forming the metal film 21 by plating. Thus, the metal film 21 can be formed without forming the metal layer 20 on the side wall of the opening 18. Consequently, the generation of voids in the via plug 21 a can be prevented, unlike the conventional producing method.

[0043] When the material A is metal nitride, the producing method of the present invention further may include a process of nitriding the surface of the barrier layer 19 after forming the barrier layer 19 and before forming the metal layer 20. This process can be, for example, heat-treatment in a nitrogen atmosphere, laser irradiation in a nitrogen atmosphere, nitrogen implantation or nitrogen plasma processing. This process makes it possible to further raise the rest potential of the surface of the barrier layer 19. For example, by heat-treating a barrier layer made of titanium nitride in the nitrogen atmosphere at 450° C. for five minutes, the rest potential value with respect to copper can be brought up to about 290 mV to 300 mV (from the pre-treatment value of about 260 mV to 265 mV).

[0044] The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed in this application are to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein. 

What is claimed is:
 1. A method for producing a semiconductor device comprising processes of: (i) forming a wiring line above a semiconductor substrate; (ii) forming an insulating layer above the semiconductor substrate and the wiring line; (iii) forming an opening penetrating the insulating layer in the insulating layer with respect to a portion above the wiring line; (iv) forming a barrier layer whose surface is formed of a material A, so as to cover a surface of the insulating layer and an inner surface of the opening; (v) forming a metal layer made of a first metal on the barrier layer; and (vi) depositing a second metal inside the opening by a plating, thus forming a via plug containing the second metal; wherein a rest potential P_(A) of the material A with respect to the second metal is larger than a rest potential P_(M) of the first metal with respect to the second metal.
 2. The method according to claim 1 , wherein the barrier layer comprises a first layer and a second layer formed on the first layer; the second layer being made of the material A, and the first layer being made of a material B that has a smaller diffusion coefficient for the first metal and the second metal than the material A.
 3. The method according to claim 1 , wherein the plating is an electroplating, and in the process (v), the metal layer is formed in a portion above the insulating layer and at a bottom of the opening alone.
 4. The method according to claim 1 , wherein the material A is metal nitride, and the method further comprises a process of nitriding a surface of the barrier layer after the process (iv) and before the process (v).
 5. The method according to claim 1 , wherein the first metal and the second metal are copper.
 6. The method according to claim 1 , wherein the material A is titanium nitride.
 7. The method according to claim 6 , wherein the material B is tantalum or tantalum nitride. 